On a Low-Power High-Speed MAP Turbo Decoder Design

Turbo codes have become part of the third generation W-CDMA systems because of their extraordinary coding performance. However, decoder implementation in commercial systems suffers from power, latency and complexity limitations. Here, we address new optimization techniques to overcome these problems. This paper makes two contributions. First, SISO block is designed in a pipeline approach which increases the speed about two times. Second, it is shown that using a circuit block instead of memory for generating the interleaved addresses, reduces the power and area exponentially as the interleaver length increases. Key-Words: turbo decoder, MAP algorithm, low power, interleaver, SISO, ACS